1. Field of the Invention
The present invention relates to communication receivers and more particularly to a method and apparatus for synchronizing digitally encoded data received by the communication receiver.
2. Background Discussion
Communications systems in general and paging systems in particular using selective call signalling have attained widespread use for calling a selected paging system receiver by transmitting information from a base station transmitter to the paging receiver. Modern paging receivers have achieved multifunction capability through the use of microprocessors which allow the paging receiver to respond to information having various combinations of tone, tone and voice, or digital encoded data messages. This information is transmitted using any number of paging coding schemes and message formats.
While there are several tone only and tone and voice signal decoding systems, the decoding of such information is generally not as difficult or as demanding as decoding those signals which use digitally encoded signals. Such digital systems are capable of a high volume of messages transmitted per unit of time because of the faster information rate they can transmit for addressing individual paging devices.
The digital information which is sent out in a digital communication system normally comprises a binary signal train which includes level transitions from a first level to a second level. These levels indicate the distinction between a binary zero and a binary one. It must also be a specific time duration which corresponds to a bit interval. The non-return-to-zero (NRZ) binary coding system generally used does not delineate bit intervals. It, therefore, is necessary to ascertain when an information bit begins or ends. Because of the variability of the nature of the information and an NRZ serial binary pulse train, several bit intervals could pass without the occurrence of a transition in the signal levels. Thus, it is generally not obvious from the information received at the receiver precisely when a bit interval begins or ends.
In digital paging systems, data are sent to a particular paging receiver by transmitting the paging receiver's unique address code followed by message data. These paging receivers are normally equipped with a microprocessor for decoding the data and with battery saver circuits which activate the receiver for periodic intervals of time for decreasing battery drain and increasing the battery life of the paging receiver. To keep the activation period of the battery at a minimum, these paging systems are synchronized to allow the receiver to precisely determine when information intended for the specific receiver is transmitted.
Additionally, the transmitter and receiver must be in synchronization so that bit address sequences and frames delineating information can be correctly decoded. Ideally, it is desirable to generate a timing signal which precisely corresponds to the occurrence of the center of the bit interval. The alignment between the timing signal and the center of the bit is crucial for proper decoding of the paging information.
In these paging systems, preamble information including address and synchronization signals is transmitted before message data. The preamble is typically transmitted at a slower transmission rate while the message data are transmitted at a faster transmission rate. Previous methods to synchronize the system, such as that in U.S. Pat. No. 4,414,676, sample the preamble at five times per bit. Thus, the initial phase alignment between the digital signals and the timing of the decoding means is only known within one fifth of a bit. This is typically satisfactory for decoding data at the slower preamble transmission rate. However, decoding the message data at a faster transmission rate causes misalignment which may result in the decoding means either dropping a received bit or adding an extra unwanted bit or decreasing the probability of correctly sampling the bit when noise is present. Furthermore, since synchronization occurs at the slower transmission rate, the faster transmission rate is constrained to an upper limit determined by the synchronization to the slower transmission rate so as to prevent dropping or adding bits.
Furthermore, slight differences between the frequencies of the transmitting and receiving clocks cause further misalignments which further increases the probability of the decoding means either dropping a received bit or adding an extra unwanted bit or decreasing the probability of correctly sampling the bit when noise is present. The longer the message is, the higher the probability that the transmitting and receiving clocks will eventually become misaligned. This problem is further magnified by a difference in the synchronization signal transmission rate and the data information transmission rate.
To partially overcome these problems, highly accurate clock circuits can be utilized in both the transmitter and receiver circuits, however, these are usually prohibitive because of cost, power available in the paging receiver, and initial frequency alignment problems. Operating the transmitter and receiver in different temperature environments can also cause their respective clock frequencies to drift apart.